Intel CONTROLLERS 413808 - Manual (Page 112)

Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
112 Order Number: 317805-001US
2.7.6.2 Inbound Read Completion or Inbound Configuration Write Completion
Message
The ATU encounters this error only in the PCI-X mode.
A target abort is signaled when the target of the transaction simultaneously deasserts
DEVSEL# , deasserts TRDY#, and asserts STOP# .
When the ATU is signaled a Target-Abort while initiating either a Split Read Completion
Transaction or a Split Write Completion Message, the ATU discards the Split Completion
and take no further action
2.7.6.3 Target-Aborts Signaled by the ATU as a Target
2.7.6.3.1 Internal Bus Master Abort
A target abort can be signaled by the ATU during an inbound read request where the
internal bus cycle resulted in a master abort on the Internal Bus.
Please see
Section 2.7.9.1, “Master Abort on the Internal Bus” on page 115 for details
on the ATU response to an Internal Bus Master Abort.
2.7.6.3.2 Internal Bus Target Abort
A target abort can be signaled by the ATU during an inbound read request where the
internal bus cycle resulted in a Target Abort from the memory controller due to a
non-recoverable multi-bit ECC error.
Please see
Section 2.7.9.2, “Target Abort on the Internal Bus” on page 117 for details
on the ATU response to an Internal Bus Target Abort.
2.7.6.3.3 Inbound EROM Memory Write
Since the EROM memory window is defined to be read-only by the PCI Local Bus
Specification, Revision 2.3, the ATU target-aborts when an inbound write transaction is
claimed by the EROM memory window.
The following additional actions with the given constraints are performed by the ATU
when a target abort is signaled by the PCI target interface during an inbound EROM
Memory write transaction:
• Set the Target Abort (target) bit (bit 11) in the ATUSR.
— When the ATU PCI Target Abort (target) Interrupt Mask bit in the ATUIMR is
clear, set the PCI Target Abort (target) bit in the ATUISR. When set, no action.