Intel CONTROLLERS 413808 - Manual (Page 565)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 565
Interrupt Controller Unit—Intel
®
413808 and 413812
10.0 Interrupt Controller Unit
This chapter describes the Intel
®
413808 and 413812 I/O Controllers in TPER
Mode(4138xx) Interrupt Controller Unit. Operation modes, setup, external memory
interface, and implementation of interrupts are described in this chapter.
infrastructure
10.1 Overview
The interrupt control unit manages interrupt routing and interrupt sources to the Intel
XScale
®
processor.
interrupts are events causing a temporary break in program execution so the processor
can handle another task. Interrupts commonly request I/O services or synchronize the
processor with some external hardware activity. For interrupt handler portability across
Intel XScale
®
microarchitecture family (ARM* architecture compliant), the architecture
defines a consistent exception handling mechanism. To manage exceptions which
include interrupt requests in parallel with processor execution, the 4138xx provides an
on-chip programmable interrupt controller.
Requests for interrupt service come from many sources and are prioritized such that
instruction execution is redirected only when an exception interrupt request is of higher
priority than that of the executing task. On the 4138xx, interrupt requests may
originate from external hardware sources, internal peripherals or software. The 4138xx
contains a number of integrated peripherals which may generate interrupts, including
the following:
The interrupt controller unit can also forward interrupts to the PCI interrupt pins
( P_INT[D:A]# ) when the PCI-X interface is being used as an endpoint. Interrupts are
detected with the chip 8-bit interrupt port, an 8-bit GPIO port, and with a dedicated
High-Priority Interrupt ( HPI# ) input. Interrupt requests originate from software by the
SWI instruction. Ultimately, all interrupt sources that are steered to the Intel XScale
®
processor processor are combined into one of two internal interrupt exceptions: IRQ
and FIQ.
• SRAM DMA Unit • SRAM DMA
• UART 0 and 1 • I
2
C Bus Interface Units 0, 1 and 2
• Peripheral Bus Interface Unit • ATU-X
• Performance Monitoring Unit • Messaging Unit
• ATU-E • SRAM Memory Controller Unit
• TPMI Unit 0 • Timer 0, Timer 1 and Watch Dog
Timer
a
a. Per Intel XScale ® processor