Intel CONTROLLERS 413808 - Manual (Page 638)

Intel ® 413808 and 413812—Timers
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
638 Order Number: 317805-001US
11.4.5 Timer Interrupt Status Register – TISR
The Timer Interrupt Status Register (TISR; Table 424 ) is a three-bit register that
contains the timer’s pending interrupt status and the Watchdog pending interrupt
status (when enabled). The setting of these status bits represents the assertion of a
“level-sensitive” interrupt request to the Interrupt Controller Unit. After the interrupt
service routine completes processing of the interrupt request, it needs to write a ‘1’ to
the appropriate bit in the TISR to clear the pending request.
TISR interrupt requests are cleared after hardware or software reset.
Table 424. Timer Interrupt Status Register
–
TISR
31:03 0000 0000H Reserved.
02 0
2
Watchdog Timer Interrupt Pending — When set, there is an interrupt pending from the Watchdog
timer. This occurs when Watchdog Timer detects a zero count in WDT. After servicing the interrupt,
SW needs to write a ‘1’ to this bit to clear the pending request. Note that the Watchdog timer must
be setup to generate an interrupt. Refer to Section 426, “Watch Dog Timer Setup Register —
WDTSR” on page 639 .
01 0
2
Timer 1 Interrupt Pending — When set, there is an interrupt pending from Timer 1. This occurs when
Timer 1 detects a zero count in TCR1. After servicing the interrupt, SW needs to write a ‘1’ to this bit
to clear the pending request.
00 0
2
Timer 0 Interrupt Pending — When set, there is an interrupt pending from Timer 0. This occurs when
Timer 0 detects a zero count in TCR0. After servicing the interrupt, SW needs to write a ‘1’ to this bit
to clear the pending request.
MMR
CP
28 24 20 16 12 8 4 0 31
rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rv rc rc rc
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor
Coprocessor address
TISR: CP6, Page 9, Register 6