Intel CONTROLLERS 413808 - Manual (Page 773)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 773
Clocking and Reset—Intel ® 413808 and 413812
17.2.7 Intel XScale
®
Processor Reset Mechanism
This reset is initiated through:
• the HOLD_X0_IN_RST# / HOLD_X1_IN_RST# straps
• the ATUX — Section 2.14.41, “PCI Configuration and Status Register - PCSR” on
page 178
• the ATUE — Section 3.17.41, “PCI Configuration and Status Register - PCSR” on
page 327 .
Once invoked, the Intel XScale
®
processors are held in reset until released by software
The HOLD_X0_IN_RST# / HOLD_X1_IN_RST# are sampled at the trailing edge of
the fundamental resets and control the default value of the Core Processor Reset bits in
function 0. When invoked via the strap, software should clear the Core Processor Reset
bits in function 0 to bring the Intel XScale
®
processor out of reset.
After the initial boot sequence, the host driver can place the Intel XScale
®
processor in
reset by asserting the Initiate Core Reset bits in any of the enabled functions which
causes the corresponding Core Processor Reset bits to be set. Software must clear the
Core Processor Reset bits in the same function in order to bring the Intel XScale
®
processor out of reset.
Table 512. Core Reset Control Bit Locations
Unit Core Processor Reset Initiate Core Reset
ATUE PCSR[1:0] PCSR[9:8]
ATUX PCSR[1:0] PCSR[31:30]