Intel CONTROLLERS 413808 - Manual (Page 232)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
232 Order Number: 317805-001US
Figure 23. ATU Queue Architecture Block Diagram
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Inbound Posted Data Queue
(IPDQ) 4KBytes
Inbound Completion Data Queue
( ICPLDQ) KBytes*
Inbound Completion Header Queue
( ICPLHQ) 32 Entries*
Inbound Posted Header Queue
(IPHQ) 16 Entries
Inbound Non Posted Header
( INPHQ) 8 Entries
Outbound Posted Data Queue
( OPDQ) 4KBytes
Outbound Completion Data Queue
( OCPLDQ) 4KBytes
Outbound Completion Header Queue
( OCPLHQ) 8 Entries
Outbound Posted Header Queue
( OPHQ) 4 Entries
Non Posted Data Queue
( ONPDQ) 1 Entry
In
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In
te
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ce In
te
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al
B
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PC
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Outbound Non Posted Header
( ONPHQ) 8 Entries
Non Posted Data Queue
(INPDQ) 1 Entry
B6333-01
Note: As an endpoint, the ATU advertises infinite completion header
and completion date credits. The actual data space is 4KBytest and
supports up to 32 outstanding read requests.