3 clock requirements, Figure 48. clock structure, 48 clock structure – Intel CONTROLLERS 413808 User Manual
Page 462
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Intel
®
413808 and 413812—SGPIO Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
462
Order Number: 317805-001US
6.3
Clock Requirements
4138xx generates and drives three clock signals that are used to run the various blocks
of the SGPIO units.
• SClock - is the output clock of the SGPIO interface and runs at a fixed 99.8 KHz.
• Load Clock - this clock is used internally to load the internal latches. This clock runs
at 1/24 the SClock rate.
• Blink Generator Clock - this clock is used to drive the blink generator. This clock
runs at 1/12500 of the SClock rate.
shows the clock structure.
Figure 48. Clock Structure
1/334
1/24
1/12500
Drives Latches
Blink Rate
Generator
8 Hz
SClock
33 MHz
99.8 KHz
B6347-01
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