Intel CONTROLLERS 413808 - Manual (Page 400)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
400 Order Number: 317805-001US
Figure 39. PCI Memory Map
Outbound Doorbell Register
Inbound Message Register 0
Inbound Message Register 1
Outbound Message Register 0
Outbound Message Register 1
Inbound Doorbell Register
Inbound Interrupt Status Register
Inbound Interrupt Mask Register
4 Message Registers
0000H
0004H
0008H
000CH
0010H
001CH
0018H
0014H
0020H
0FFCH
reserved
reserved
reserved
reserved
0024H
0028H
002CH
Outbound Interrupt Status Register
Outbound Interrupt Mask Register
Reserved
2 Doorbell Registers and
0034H
0038H
003CH
0040H Reserved
Reserved
Reserved
2 Queue Ports
0044H
0048H
004CH
0050H
0030H
4 Interrupt Registers
Reserved
MSI Inbound Message Register
Offsets are relative to the MU Base Address Registers (MUBAR/MUUBAR)
Offset
MSI-X Table
MSI-X PBA
1000H
17FCH
1800H
1FFCH
8 Entries
1 Register
Reserved
Reserved
B6621-01
Note: The MU always claim the entire 8 KBytes of the internal bus address space
relative to the MU Base Address Registers. The 8 KBytes include the MU Registers,
and MSI-X Data Structures. See more detailed descriptions under Section 311, “MU
Base Address Register - MUBAR” on page 81.
Reserved