Intel CONTROLLERS 413808 - Manual (Page 143)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 143
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.2 Internal Bus Registers
A subset of the ATU registers are accessible through both inbound PCI configuration
cycles and the 4138xx core CPU (Register offsets 000H through 0FFH). The balance of
the registers are accessible only via the internal bus. Table 26, “Address Translation
Unit Registers” on page 143 represents all of the ATU registers.
The location of these registers are specified as a relative offset to a 512KB aligned
global PMMR offset. The default for the 512KB aligned offset is 0 FFD8 0000H defined
by the PMMRBAR register. See also Chapter 19.0, “Peripheral Registers” .
The Internal Bus Address Offset to PMMRBAR of any ATU Register can be derived by
adding the 4 KB address aligned Internal Bus Memory Mapped Register Range Offset
( Table 27, “ATU Internal Bus Memory Mapped Register Range Offsets” on page 146 ) to
the Register Offset ( Table 26, “Address Translation Unit Registers” on page 143 )
For example, when INTERFACE_SEL_PCIX# and CONTROLLER_ONLY# are both
asserted, the offset to PMMRBAR of the
“ATU Command Register - ATUCMD”
would be
(4 C000H+004H) or 4 C004H.
Note: The 4 KB Address Aligned Range Offset can be different depending on two configuration
straps as described in Table 27 .
Table 26. Address Translation Unit Registers (Sheet 1 of 3)
Register
Offset
ATU Register Section, Name, Page
000H Section 2.14.3, “ATU Vendor ID Register - ATUVID” on page 147
002H Section 2.14.4, “ATU Device ID Register - ATUDID” on page 147
004H Section 2.14.5, “ATU Command Register - ATUCMD” on page 148
006H Section 2.14.6, “ATU Status Register - ATUSR” on page 149
008H Section 2.14.7, “ATU Revision ID Register - ATURID” on page 151
009H Section 2.14.8, “ATU Class Code Register - ATUCCR” on page 151
00CH Section 2.14.9, “ATU Cacheline Size Register - ATUCLSR” on page 152
00DH Section 2.14.10, “ATU Latency Timer Register - ATULT” on page 152
00EH Section 2.14.11, “ATU Header Type Register - ATUHTR” on page 153
00FH Section 2.14.12, “ATU BIST Register - ATUBISTR” on page 154
010H Section 2.14.13, “Inbound ATU Base Address Register 0 - IABAR0” on page 155
014H Section 2.14.14, “Inbound ATU Upper Base Address Register 0 - IAUBAR0” on page 156
018H Section 2.14.15, “Inbound ATU Base Address Register 1 - IABAR1” on page 157
01CH Section 2.14.16, “Inbound ATU Upper Base Address Register 1 - IAUBAR1” on page 158
020H Section 2.14.17, “Inbound ATU Base Address Register 2 - IABAR2” on page 159
024H Section 2.14.18, “Inbound ATU Upper Base Address Register 2 - IAUBAR2” on page 160
02CH Section 2.14.19, “ATU Subsystem Vendor ID Register - ASVIR” on page 161
02EH Section 2.14.20, “ATU Subsystem ID Register - ASIR” on page 161
030H Section 2.14.21, “Expansion ROM Base Address Register - ERBAR” on page 162
034H Section 2.14.22, “ATU Capabilities Pointer Register - ATU_Cap_Ptr” on page 163
03CH Section 2.14.24, “ATU Interrupt Line Register - ATUILR” on page 166
03DH Section 2.14.25, “ATU Interrupt Pin Register - ATUIPR” on page 167
03EH Section 2.14.26, “ATU Minimum Grant Register - ATUMGNT” on page 167
03FH Section 2.14.27, “ATU Maximum Latency Register - ATUMLAT” on page 168
040H Section 2.14.28, “Inbound ATU Limit Register 0 - IALR0” on page 169
044H Section 2.14.29, “Inbound ATU Translate Value Register 0 - IATVR0” on page 170