Intel, Bit default description, Reserved – Intel CONTROLLERS 413808 User Manual

Page 452: Channel # intel xscale

Advertising

Intel

413808 and 413812—SRAM DMA Unit (SDMA)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

452

Order Number: 317805-001US

5.4.7

LocalToHost Byte Swap Control Register - L2H_BSCR

The LocalToHost Byte SWap Control Register (L2H_BSCR) provides the control to

enable/disable byte swapping.

Note:

The “Default” enables byte swapping.

5.4.8

HostToLocal Destination Lower Address Register - H2L_DLAR

The HostToLocal Destination Lower Address Register - H2L_DLAR represents the local

memory address.

Table 305. LocalToHost Byte Swap Control Register - L2H_BSCR

Bit

Default

Description

Reserved.

Byte Swap Disable - Read/Write

This bit must be set to prevent SDMA transfers from byte swapping.

29:0

Reserved.

Coprocessor

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal bus address offset

18200H

Table 306. HostToLocal Destination Lower Address Register - H2L_DLAR

Bit

Default

Description

31:20

000H

Reserved

19:00

00000H

Destination Lower Address Register (DLAR) - Read/Write

This field specifies the destination (local) memory starting byte address that the SDMA Processor uses

to write data. The field decodes a 1MB local memory address space that represents of the offset from

the base of SRAM.

Coprocessor

IOP

Attributes

Channel #

Intel XScale

Microarchitecture internal bus address offset

1825CH