Intel CONTROLLERS 413808 - Manual (Page 386)

Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
386 Order Number: 317805-001US
3.17.107 Inbound Vendor Message Header Register 2 - IVMHR2
The Inbound Vendor Message Header Registers capture the header for a vendor defined
message received on the PCI Express interface. Once the inbound message has been
processed, the Inbound Vendor Message Received bit is set in the ATU Interrupt Status
Register - ATUISR . Subsequent inbound vendor messages are held in the inbound
posted queues until the status bit is cleared or the mask bit is set in the ATU Interrupt
Mask Register - ATUIMR . When the mask bit is set, then Vendor_Defined Type 0
messages are treated as unsupported requests and Vendor_Defined Type 1 messages
are silently discarded.
Table 247. Inbound Vendor Defined Message Header Register 2 - IVMHR2
Bit Default Description
31:24 00H Header Byte 8
23:16 00H Header Byte 9
15:8 00H Header Byte 10
7:0 00H Header Byte 11
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+348H