Intel CONTROLLERS 413808 - Manual (Page 539)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 539
SRAM Memory Controller—Intel
®
413808 and 413812
19:16 0000
2
Direct Memory Port ID: Indicates the direct memory port associated with the ECC logged
error.
Port ID Port Name
0000
2
North Internal Bus Port
0001
2
Reserved
0010
2
Reserved
0011
2
Reserved
0100
2
Reserved
0101
2
Reserved
0110
2
Reserved
0111
2
Reserved
1000
2
Reserved
1001
2
Reserved
1010
2
Reserved
All other IDs are reserved.
15:13 000
2
Reserved
12 0
2
Read or Write : Indicates if the error occurred during a read or write transaction.
0 = Read error
1 = Write Error
11:09 000
2
Reserved
08 0
2
ECC Error Type: Indicates the type of error that occurred at this address.
0 = Single Bit Error
1 = Multi-Bit Error
07:00 00H Syndrome: Holds the syndrome value that indicated the error.
Table 353. SRAM ECC Log Register — SELOG (Sheet 2 of 2)
Bit Default Description
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
rv
na
rv
na
rv
na
ro
na
rv
na
rv
na
rv
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
ro
na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Local Bus Address Offset
+150CH