58 ecc first address register - eccfar, Table 85. ecc first address register - eccfar, 58ecc first address register - eccfar – Intel CONTROLLERS 413808 User Manual

Page 198: 85 ecc first address register - eccfar, Ecc first, Ecc first address register - eccfar, P_ad[31:0, Intel, Bit default description

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Intel

413808 and 413812—Address Translation Unit (PCI-X)

Intel

413808 and 413812 I/O Controllers in TPER Mode

Developer’s Manual

October 2007

198

Order Number: 317805-001US

2.14.58 ECC First Address Register - ECCFAR

When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating

that an error has been captured), the ECCFAR register indicates the contents of the

P_AD[31:0]

bus (for 64- and 32-bit buses) for the address phase of the transaction

that included the error. For Dual Address Cycle (DAC) transactions, this represents the

least significant 32-bits of the 64-bit address. When the ECC Error Phase register is

zero, the contents of this register are undefined.

Note:

Registers that store information from the failing transaction always store information

directly from the bus (uncorrected), even when correction of the error is possible.

Note:

The

“ECC Control and Status Register - ECCCSR”

“ECC First Address Register -

ECCFAR”

“ECC Second Address Register - ECCSAR”

, and

“ECC Attribute Register -

ECCAR”

report the actual transaction that has the error. For example, when the Split

Completion of an original Outbound Read request has an error, the information

regarding the Split Completion is reported.

Table 85. ECC First Address Register - ECCFAR

Bit

Default

Description

31:00 0000 0000H

ECC First Address - This register represents the 32-bit address of a failing single address cycle (SAC)

transaction. Or, in the case of a failing DAC transaction, this register represents the least significant

32-bits of the address.

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address

+0DCH

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