Intel CONTROLLERS 413808 - Manual (Page 677)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 677
UARTs—Intel ® 413808 and 413812
4 0
2
Even Parity Select (EPS): When PEN is set (1) and EPS is clear (0), an odd
number of logic ones is transmitted or checked in the data word bits and the parity
bit. When PEN is set (1) and EPS is also set (1), an even number of logic ones is
transmitted or checked in the data word bits and parity bit. When PEN = 0, EPS is
ignored.
0 = sends or checks for odd parity.
1 = sends or checks for even parity.
3 0
2
Parity Enable (PEN): When set (1), a parity bit is generated (transmit data) or
checked (receive data) between the last data word bit and Stop bit of the serial data.
(The parity bit is used to produce an even or odd number of ones when the data
word bits and the parity bit are summed.)
0 = no parity function.
1 = allows parity generation and checking.
2 0
2
Stop bits (STB): This bit specifies the number of stop bits transmitted and received
in each serial character. When STB is clear (0), one stop bit is generated in the
transmitted data. When STB is set (1) when a 5-bit word length is selected via
WLS[1:0], then 1 and one half stop bits are generated. When STB is set (1) when
either a 6, 7, or 8-bit word is selected, then two stop bits are generated. The receiver
checks the first stop bit only, regardless of the number of stop bits selected.
0 = 1 stop bit
1 = 2 stop bits, except for 5-bit character then 1-1/2 bits
1:0 00
2
Word Length Select (WLS[1:0]): Specifies the number of data bits in each
transmitted or received serial character.
00 = 5-bit character (default)
01 = 6-bit character
10 = 7-bit character
11 = 8-bit character
Table 453. UART x Line Control Register - (UxLCR) (Sheet 2 of 2)
Bit Default Description
P
C
I
IO
P
A
tt
ri
b
u
te
s
A
tt
ri
b
u
te
s
28 24 20 16 12 8 4 0 31
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Unit #
01
Intel XScale ® Core internal bus address
+230CH (DLAB=x)
+234CH (DLAB=x)
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible