Intel CONTROLLERS 413808 - Manual (Page 448)

Intel
®
413808 and 413812—SRAM DMA Unit (SDMA)
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
448 Order Number: 317805-001US
5.4.3 LocalToHost Source Lower Address Register - L2H_SLAR
The LocalToHost Source Lower Address Register (L2H_SLAR) represents the lower 32
bits of the source (local) address. The upper address bits are zero, as local memory is
limited to 1 Mbyte.
Table 301. LocalToHost Source Lower Address Register - L2H_SLAR
Bit Default Description
31:20 000H Reserved. Must be written as zero.
19:00 00000H
Source Lower Address Register (SLAR) - Read/Write
Specifies first source (local) memory starting byte address that SDMA Processor uses to read data. The
field decodes a 1MB local memory address space that represents of the offset from the base of SRAM.
Coprocessor
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
pr
na
pr
na
rw
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rv
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
rw
na
Intel XScale ® Microarchitecture internal bus address offset
1820CH
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible