31 mu msi-x control register x - mmcrx, Table 296. mu msi-x control register x - mmcrx, 31 mu msi-x control register x — mmcrx – Intel CONTROLLERS 413808 User Manual
Page 440: 296 mu msi-x control register x — mmcrx, Mu msi-x control register x — mmcrx” on, Table 296. mu msi-x control register x — mmcrx, Intel, Bit default description
Intel
®
413808 and 413812—Messaging Unit
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
440
Order Number: 317805-001US
4.7.31
MU MSI-X Control Register X — MMCRx
By default, the MU can generate up to eight MSI-X messages. The MMCRx register
provides a control bit that allows collapsing the eight MSI-X messages down to only a
single message. When the Host processor cannot honor the eight requested MSI-X
messages, the MU MSI-X Single Message Vector bit can be set to cause only a single
MSI-X message to be generated.
Table 296. MU MSI-X Control Register X — MMCRx
Bit
Default
Description
31:01
0000 0000H Reserved
00
0
2
MU MSI-X Single Message Vector: This bit when set, causes only a single MSI-X Message to be
generated when MSI-X is enabled. This bit affects the default value of the MSI-X Table Size field in the
MSI-X Message Control Register - MSI-X_MCR
.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0BCH