Intel CONTROLLERS 413808 - Manual (Page 23)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 23
Contents—Intel
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413808 and 413812
105 General Call Address .............................................................................................. 707
106 Example Block Diagram of Component with Counter ................................................... 729
107 Conceptual Diagram of Counter Array ....................................................................... 730
108 Example Block Diagram of Single PMON Counter ....................................................... 731
109 Flowchart of Example Commands Sequence............................................................... 732
110 Block Diagram and Waveforms of Time Based Sampling Example ................................. 733
111 Block Diagram and Waveforms of Time Based Sampling Example ................................. 735
112 Block Diagram & Waveforms of Time Based Sampling Example .................................... 736
113 Block Diagram & Waveforms of Time Based Sampling Example .................................... 737
114 Block Diagram of HOQ Histogram Example ................................................................ 740
115 Waveforms of HOQ Histogram Example..................................................................... 741
116 Processing of HOQ Histogram Example...................................................................... 742
117 Output from HOQ Histogram Example....................................................................... 742
118 Indicator Tree........................................................................................................ 744
119 Intel
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413808 and 413812 I/O Controllers in TPER Mode Clocking Regions Diagram ....... 763
120 IEEE 1149.1 Std. Block Diagram .............................................................................. 783
121 Timing of Actions in a TAP Controller State ................................................................ 785
122 TAP Controller State Diagram .................................................................................. 785
123 IOP Device ID Register ........................................................................................... 792
124 Intel
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413808 and 413812 I/O Controllers in TPER Mode Memory Address Space........... 797