Intel CONTROLLERS 413808 - Manual (Page 673)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 673
UARTs—Intel ® 413808 and 413812
Table 451. Interrupt Identification Register Decode
Interrupt ID bits Interrupt SET/RESET Function
3 2 1 0 Priority Type Source RESET Control
IP# 0 0 0 1 - None No Interrupt is pending. -
IID[11] 0 1 1 0 Highest
Receiver Line
Status
Overrun Error, Parity Error,
Framing Error, Break
Interrupt.
Reading the Line Status
Register.
IID[10] 0 1 0 0
Second
Highest Received Data
Available.
Non-FIFO mode: Receive
Buffer is full. Non-FIFO mode: Reading the
Receiver Buffer Register.
FIFO mode: Trigger level
was reached.
FIFO mode: Reading bytes until
Receiver FIFO drops below
trigger level or setting
RESETRF bit in FCR register.
TOD 1 1 0 0
Second
Highest
Character
Timeout
indication.
FIFO Mode only: At least 1
character is in receiver FIFO
and there was no activity for
a time period.
Reading the Receiver FIFO or
setting RESETRF bit in FCR
register.
IID[01] 0 0 1 0
Third
Highest Transmit FIFO
Data Request
Non-FIFO mode: Transmit
Holding Register Empty
Reading the IIR Register (when
the source of the interrupt) or
writing into the Transmit
Holding Register.
FIFO mode: Transmit FIFO
has half or less than half
data. Reading the IIR Register (when
the source of the interrupt) or
writing to the Transmitter FIFO.
IID[00] 0 0 0 0
Fourth
Highest
Modem Status
Clear to Send, Data Set
Ready, Ring Indicator,
Received Line Signal Detect
Reading the Modem Status
Register.
Non Prioritized Interrupts
ABL 4 None
Autobaud Lock
Indication Autobaud circuitry has
locked onto the baud rate.
Reading the IIR Register