Intel CONTROLLERS 413808 - Manual (Page 580)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
580 Order Number: 317805-001US
10.6 Default Status
The interrupt logic is reset by the PCI reset signal or through software. Table 381 shows
the power-up and reset values.
Table 381. Default Interrupt Routing and Status Values
Register Default Value Description
INTCTL0 0000 0000H All interrupts 31:0 masked.
INTCTL1 0000 0000H All interrupts 63:32 masked.
INTCTL2 0000 0000H All interrupts 95:64 masked.
INTCTL3 0000 0000H All interrupts 127:96 masked.
INTSTR0 0000 0000H All interrupts 31:0 steered to IRQ.
INTSTR1 0000 0000H All interrupts 63:32 steered to IRQ.
INTSTR2 0000 0000H All interrupts 95:64 steered to IRQ.
INTSTR3 0000 0000H All interrupts 127:96 steered to IRQ.
IINTSRC0 0000 0000H All IRQ interrupts 31:0 inactive.
IINTSRC1 0000 0000H All IRQ interrupts 63:32 inactive.
IINTSRC2 0000 0000H All IRQ interrupts 95:64 inactive.
IINTSRC3 0000 0000H All IRQ interrupts 127:96 inactive.
FINTSRC0 0000 0000H All FIQ interrupts 31:0 inactive.
FINTSRC1 0000 0000H All FIQ interrupts 63:32 inactive.
FINTSRC2 0000 0000H All FIQ interrupts 95:64 inactive.
FINTSRC3 0000 0000H All FIQ interrupts 127:96 inactive.
IPR0 0000 0000H All interrupts 15:0 at Priority 0.
IPR1 0000 0000H All interrupts 32:16 at Priority 0.
IPR2 0000 0000H All interrupts 47:33 at Priority 0.
IPR3 0000 0000H All interrupts 63:48 at Priority 0.
IPR4 0000 0000H All interrupts 79:64 at Priority 0.
IPR5 0000 0000H All interrupts 95:80 at Priority 0.
IPR6 0000 0000H All interrupts 111:96 at Priority 0.
IPR7 0000 0000H All interrupts 127:112 at Priority 0.
Note: For the default value of a register that is not listed in this table refer to the corresponding register
section.