Intel CONTROLLERS 413808 - Manual (Page 393)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 393
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.116 PCI Interface Error Status - PIE_STS
The PCI Interface Error Status register reports error status of individual uncorrectable
error sources. An individual error status bit that is set to “1” indicates that a particular
error occurred; software may clear an error status by writing a 1 to the respective bit.
Note: The status bits are set even when the reporting of the error is masked in the PIE_MSK
register.
Table 256. PCI Interface Error Status - PIE_STS
Bit Default Description
31 0 Received Completion with Unsupported Request Status
30 0 Received Completion with Completer Abort Status
29 0 Poisoned TLP Transmitted Status
28 0 Transmit: Header Parity Error detected
27:21 0 Reserved Zero - Software must write 0 to these bits.
20 0
Unsupported Request Error Status - As a receiver, Set whenever an unsupported request is detected.
The Header is logged.
19 0 ECRC Check - As a receiver, set when ECRC check fails. The Header is logged.
18 0 Malformed TLP: As a receiver, set whenever a malformed TLP is detected. The Header is logged.
17 0 Receiver Overflow: Set when PCI Express receive buffers overflow.
16 0
Unexpected Completion: As a receiver, set whenever a completion is received that does not match the
4138xx’s requestor ID or outstanding Tag. The Header is logged.
15 0
Completer Abort: As a completer, set whenever an internal agent signals a data abort. The header is
logged.
14 0
Completion Timeout: As a requester, set whenever an outbound Non Posted Request does not receive a
completion within 16-32ms.
13 0 Flow Control Protocol Error Status: Set whenever a flow control protocol error is detected.
12 0
Poisoned TLP Received: As a receiver, set whenever a poisoned TLP is received from PCI Express. The
header is logged.
11:5 0 Reserved Zero - Software must write 0 to these bits.
4 0 Data Link Protocol Error: Set whenever a data link protocol error is detected.
3:1 0 Reserved Zero - Software must write 0 to these bits.
0 0 Training Error - Set whenever a training error is detected.
PCI
IOP
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rc
rc
rc
rc
rc
rc
rc
rc
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rz
rc
rc
rz
rz
rz
rz
rz
rz
rc
rc
Attribute Legend:
RZ = Reserved Zero
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+384H