Intel CONTROLLERS 413808 - Manual (Page 654)

Intel ® 413808 and 413812—SMBus Interface Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
654 Order Number: 317805-001US
12.3.4 Error Handling
The SMBus slave interface handles two types of errors: internal address error and PEC.
Internal address errors can occur, for example, when the SMBus request on the 4138xx
internal bus fails due to an address parity error. This error manifests itself as a
Not-Acknowledge (NACK) for the read or write command (End bit is set). Other internal
errors include the read or write command receiving a master or target abort on the
internal interface. When the master receives a NACK, the entire transaction should be
reattempted.
When the master supports packet error checking (PEC) and the PEC enable bit in the
command is set, then the PEC byte is checked in the slave interface. When the check
indicates a failure, then the slave NACKs the PEC packet and does not issue the
command on the internal interface.
An SMBus master must either do PEC on all transactions in a sequence or not do it at
all; that is, it cannot turn on PEC in the middle of a sequence.
A PEC error in the middle of a sequence must be re-started from the beginning of the
sequence; that is, the begin bit set.
12.3.5 SMBus Interface Reset
The master in two ways can reset the slave interface state machine in 4138xx:
The master holds
SMBCLK low for 25 ms cumulative. Cumulative in this case means
that all the “low time” for SMBCLK is counted between the Start and Stop bit. When
this totals 25 ms before reaching the Stop bit, the interface is reset.
The master holds
SMBCLK continuously high for 50 ms.
Besides these, the SMBus interface in 4138xx is also reset on a P_RST#, WARM_RST#
or an in-band warm reset from PCI Express*.