Section 3.17.44, Pci express message control and status, Register - pemcsr – Intel CONTROLLERS 413808 User Manual

Page 333: Address translation unit (pci express)—intel, Bit default description

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Intel

413808 and 413812 I/O Controllers in TPER Mode

October 2007

Developer’s Manual

Order Number: 317805-001US

333

Address Translation Unit (PCI Express)—Intel

413808 and 413812

3.17.44 PCI Express Message Control/Status Register - PEMCSR

The PCI Express Message Control/Status Register controls the generation and logs the

receipt of PCI Express Power Management and Hot-Plug messages.

Table 184. PCI Express Message Control and Status Register - PEMCSR

Bit

Default

Description

31:30

Attention Indicator Status

As an end point, the ATU may receive Hot-Plug Attention Indicator Control Messages. When the

message is received, the status is logged in these fields and the Hot-Plug interrupt bit is set in the

ATUISR.

Reserved

Blink

Off

Note:

These bits are updated regardless of the state of the Hot-Plug Interrupt Mask in the ATUIMR.

29:28

Power Indicator Status

As an end point, the ATU may receive Hot-Plug Power Indicator Control Messages. When the message

are received, the status is logged in these fields and the Hot-Plug interrupt bit is set in the ATUISR.

Reserved

Blink

Off

Note:

These bits are updated regardless of the state of the Hot-Plug Interrupt Mask in the ATUIMR.

27:16

000H

Reserved.

Attention Button Pressed Control

When this bit is asserted, an Attention_Button_Pressed message is generated. This bit self-clears after

the message has been transmitted. Only valid as an end point.

Inbound Vendor_Defined Type 0 Unsupported Request response

When asserted, the ATU generates an Unsupported Request response for the Message logged in the

Inbound Vendor Defined Message Registers. The contents of the IVMH registers is copied to the

Advanced Error Header Log and the unsupported request status is updated.

When the UR response is required, software must set this bit prior to clearing the Interrupt status bit in

the ATUISR.

This bit is self clearing after the UR message has been delivered.

13:0

0000H

Reserved

PCI

IOP

Attributes

Attribute Legend:

RV = Reserved

PR = Preserved

RS = Read/Set

RW = Read/Write

RC = Read Clear

RO = Read Only

NA = Not Accessible

Internal Bus Address Offset

+080H

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