Intel CONTROLLERS 413808 - Manual (Page 404)

Intel
®
413808 and 413812—Messaging Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
404 Order Number: 317805-001US
4.4 Doorbell Registers
There are two Doorbell Registers: the Inbound Doorbell Register and the Outbound
Doorbell Register. The Inbound Doorbell Register allows external PCI agents to
generate interrupts to the Intel XScale
®
processor. The Outbound Doorbell Register
allows the Intel XScale
®
processor to generate a PCI interrupt. Both Doorbell Registers
may generate interrupts whenever a bit in the register is set.
4.4.1 Outbound Doorbells
When the Outbound Doorbell Register is written by the Intel XScale
®
processor, an
interrupt may be generated on the P_INTA# interrupt pin or a message signaled
interrupt is generated when MSI is enabled. An interrupt is generated when any of the
bits in the doorbell register is written to a value of 1. Writing a value of 0 to any bit
does not change the value of that bit and does not cause an interrupt to be generated.
Once a bit is set in the Outbound Doorbell Register, it cannot be cleared by the Intel
XScale
®
processor.
The interrupt is recorded in the Outbound Interrupt Status Register.
The interrupt may be masked by the mask bits in the Outbound Interrupt Mask
Register. When the mask bit is set for a particular bit, no interrupt is generated for that
bit. The Outbound Interrupt Mask Register affects only the generation of the interrupt
and not the values written to the Outbound Doorbell Register.
The interrupt is cleared when an external PCI agent writes a value of 1 to the bits in the
Outbound Doorbell Register that are set. Writing a value of 0 to any bit does not
change the value of that bit and does not clear the interrupt.
In summary, the Intel XScale
®
processor generates an interrupt and external PCI
agents clear the interrupt by setting bits in the Outbound Doorbell Register.
4.4.2 Inbound Doorbells
When the Inbound Doorbell Register is written by an external PCI agent, an interrupt
may be generated to the Intel XScale
®
processor. An interrupt is generated when any
of the bits in the doorbell register is written to a value of 1. Writing a value of 0 to any
bit does not change the value of that bit and does not cause an interrupt to be
generated. Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by
any external PCI agent. The interrupt is recorded in the Inbound Interrupt Status
Register.
The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the
Inbound Interrupt Mask Register. When the mask bit is set for a particular bit, no
interrupt is generated for that bit. The Inbound Interrupt Mask Register affects only the
generation of the normal messaging unit interrupt and not the values written to the
Inbound Doorbell Register. One bit in the Inbound Doorbell Register is reserved for an
Error Doorbell interrupt.
The interrupt is cleared when the Intel XScale
®
processor writes a value of 1 to the bits
in the Inbound Doorbell Register that are set. Writing a value of 0 to any bit does not
change the value of that bit and does not clear the interrupt.