60 ecc attribute register - eccar, Table 87. ecc attribute register - eccar, 61 compactpci hot-swap capability id register – Intel CONTROLLERS 413808 User Manual
Page 200: Table 88. hs_capid - hot-swap cap id, 60ecc attribute register - eccar, 61compactpci hot-swap capability id register, 87 ecc attribute register - eccar, 88 hs_capid - hot-swap cap id, Section 2.14.61, “compactpci, Hot-swap capability id register
Intel
®
413808 and 413812—Address Translation Unit (PCI-X)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
200
Order Number: 317805-001US
2.14.60 ECC Attribute Register - ECCAR
When the ECC Error Phase register (bits 6:4 of the ECCCSR) is non-zero (indicating
that an error has been captured), the ECCAR register indicates the contents of the
P_AD[31:0]
bus (for 64- and 32-bit buses) for the attribute phase of the transaction
that included the error. When the ECC Error Phase register is zero, the contents of this
register are undefined.
Note:
Registers that store information from the failing transaction always store information
directly from the bus (uncorrected), even when correction of the error is possible.
Note:
“ECC Control and Status Register - ECCCSR”
“ECC Second Address Register - ECCSAR”
, and
report the actual transaction that has the error. For example, when the Split
Completion of an original Outbound Read request had an error, the information
regarding the Split Completion is reported.
2.14.61 CompactPCI Hot-Swap Capability ID Register
The following register block provides support of CompactPCI* Hot-Swap functionality.
Table 87. ECC Attribute Register - ECCAR
Bit
Default
Description
31:00 0000 0000H ECC Attribute - This register represents contents of the
P_AD[31:0]
bus (for 64- and 32-bit buses) for
the attribute phase of a failing transaction.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0E4H
Table 88. HS_CAPID - Hot-Swap Cap ID
Bit
Default
Description
07:00
06h
Identifier (ID):
06h, identifying this linked list structure as being the Compact PCI Hot-Swap register block.
PCI
IOP
Attributes
Attributes
7
4
0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
RW = Read/Write
RO = Read Only
RT = Read/Toggle
RC = Read/Clear
SW = SROM Write
NA = Not Accessible
Register Offset
+0E8H