Intel CONTROLLERS 413808 - Manual (Page 191)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 191
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.54 PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr
The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.3. This register describes the location of the next item in the
function’s capability list.
2.14.55 PCI-X Command Register - PCIXCMD
This register controls various modes and features of ATU and Message Unit when
operating in the PCI-X mode.
Table 81. PCI-X Next Item Pointer Register - PCI-X_Next_Item_Ptr
Bit Default Description
07:00 E8H
Next_ Item_ Pointer - This field provides an offset into the function’s configuration space pointing to the
next item in the function’s capability list which in the 4138xx is the CompactPCI extended capabilities
header.
PCI
IOP
Attributes
Attributes
7 4 0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
PCI Configuration Offset
D1H
Register Offset
+0D1H
Table 82. PCI-X Command Register - PCIXCMD (Sheet 1 of 2)
Bit Default Description
15:14 00
2
Reserved
13:12 01
2
PCI-X Capabilities List Item Version - This field indicates that the 4138xx implements version 1 of the
PCI-X Capabilities list item defined in the PCI-X Protocol Addendum to the PCI Local Bus Specification,
Revision 2.0. Specifically, the 4138xx implements the 24 byte format of the PCI-X capabilities list item
and support for ECC in Mode 2 only.
11:7 00000
2
Reserved
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rv
rv
rv
rv
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+0D2H