Intel CONTROLLERS 413808 - Manual (Page 295)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 295
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
+094H Section 3.17.49, “VPD Data Register - VPDDR” on page 336
+098H Section 3.17.50, “PM Capability Identifier Register - PM_Cap_ID” on page 337
+099H Section 3.17.51, “PM Next Item Pointer Register - PM_Next_Item_Ptr” on page 337
+09AH Section 3.17.52, “ATU Power Management Capabilities Register - APMCR” on page 338
+09CH Section 3.17.53, “ATU Power Management Control/Status Register - APMCSR” on page 339
+0A0H Section 4.7.20, “MSI Capability Identifier Register - Cap_ID” on page 429 a
+0A1H Section 4.7.21, “MSI Next Item Pointer Register - MSI_Next_Ptr” on page 430 a
+0A2H Section 4.7.22, “Message Control Register - Message_Control” on page 431 a
+0A4H Section 4.7.23, “Message Address Register - Message_Address” on page 432 a
+0A8H Section 4.7.24, “Message Upper Address Register - Message_Upper_Address” on page 433 a
+0ACH Section 4.7.25, “Message Data Register- Message_Data” on page 434 a
+0B0H Section 4.7.26, “MSI-X Capability Identifier Register - MSI-X_Cap_ID” on page 435 b
+0B1H Section 4.7.27, “MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr” on page 436 b
+0B2H Section 4.7.28, “MSI-X Message Control Register - MSI-X_MCR” on page 437 b
+0B4H Section 4.7.29, “MSI-X Table Offset Register — MSI-X_Table_Offset” on page 438 b
+0B8H Section 4.7.30, “MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset” on page 439 b
+0BCJ-
+0C8H Reserved
+0CCH Section 3.17.54, “ATU Scratch Pad Register - ATUSPR” on page 340
+0D0H Section 3.17.55, “PCI Express Capability List Register - PCIE_CAPID” on page 340
+0D1H Section 3.17.56, “PCI Express Next Item Pointer Register - PCIE_NXTP” on page 341
+0D2H Section 3.17.57, “PCI Express Capabilities Register - PCIE_CAP” on page 342
+0D4H Section 3.17.58, “PCI Express Device Capabilities Register - PCIE_DCAP” on page 343
+0D8H Section 3.17.59, “PCI Express Device Control Register - PE_DCTL” on page 344
+0DAH Section 3.17.60, “PCI Express Device Status Register - PE_DSTS” on page 346
+0DCH Section 3.17.61, “PCI Express Link Capabilities Register - PE_LCAP” on page 347
+0E0H Section 3.17.62, “PCI Express Link Control Register - PE_LCTL” on page 348
+0E2H Section 3.17.63, “PCI Express Link Status Register - PE_LSTS” on page 349
+0E4H Section 3.17.64, “PCI Express Slot Capabilities Register - PE_SCAP” on page 350
+0E8H Section 3.17.65, “PCI Express Slot Control Register - PE_SCR” on page 351
+0EAH Section 3.17.66, “PCI Express Slot Status Register - PE_SSTS” on page 352
+0ECH Section 3.17.67, “PCI Express Root Control Register - PE_RCR” on page 353
+0F0H Section 3.17.68, “PCI Express Root Status Register - PE_RSR” on page 354
+100H Section 3.17.69, “PCI Express Advanced Error Capability Identifier - ADVERR_CAPID” on page 354
+104H Section 3.17.70, “PCI Express Uncorrectable Error Status - ERRUNC_STS” on page 355
+108H Section 3.17.71, “PCI Express Uncorrectable Error Mask - ERRUNC_MSK” on page 356
+10CH Section 3.17.72, “PCI Express Uncorrectable Error Severity - ERRUNC_SEV” on page 357
+110H Section 3.17.73, “PCI Express Correctable Error Status - ERRCOR_STS” on page 358
+114H Section 3.17.74, “PCI Express Correctable Error Mask - ERRCOR_MSK” on page 359
+118H Section 3.17.75, “Advanced Error Control and Capability Register - ADVERR_CTL” on page 360
+11CH Section 3.17.76, “PCI Express Advanced Error Header Log - ADVERR_LOG0” on page 360
+120H Section 3.17.77, “PCI Express Advanced Error Header Log - ADVERR_LOG1” on page 361
+124H Section 3.17.78, “PCI Express Advanced Error Header Log - ADVERR_LOG2” on page 361
+128H Section 3.17.79, “PCI Express Advanced Error Header Log - ADVERR_LOG3” on page 362
+12CH Section 3.17.80, “Root Error Command Register - RERR_CMD” on page 362
+130H Section 3.17.81, “Root Error Status Register” on page 363
Table 141. ATU PCI Configuration Register Space (Sheet 2 of 3)
Interna
l Bus
Address
Offset
ATU PCI Configuration Register Section, Name, Page