Intel CONTROLLERS 413808 - Manual (Page 593)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 593
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.10 Interrupt Control Register 1 — INTCTL1
The Interrupt Control register 1 is a 32-bit Coprocessor 6 control register used to
specify which of 32 interrupts are masked.
Table 392. Interrupt Control Register 1 — INTCTL1 (Sheet 1 of 2)
Bit Default Description
31 0
2
Reserved.
30 0
2
Messaging Unit Error Interrupt Mask
0 = Masked
1 = Not Masked
29:28 0
2
Reserved.
27 0
2
Reserved.
26 0
2
Reserved.
25 0
2
Reserved.
24 0
2
Memory Controller Unit Error Interrupt Mask
0 = Masked
1 = Not Masked
23 0
2
ATU Error Interrupt Mask
0 = Masked
1 = Not Masked
22 0
2
ATU Configuration Register Write Interrupt Mask
0 = Masked
1 = Not Masked
21 0
2
Peripheral Bus Unit Error Interrupt Mask
0 = Masked
1 = Not Masked
20 0
2
UART 1 Interrupt Mask
0 = Masked
1 = Not Masked
19 0
2
UART 0 Interrupt Mask
0 = Masked
1 = Not Masked
18:08 000H Reserved.
07 0
2
XINT15# Interrupt Mask. Source of this interrupt is the GPIO[7] pin.
0 = Masked
1 = Not Masked
06 0
2
XINT14# Interrupt Mask. Source of this interrupt is the GPIO[6] pin.
0 = Masked
1 = Not Masked
Memory
Coprocessor
Attributes
Attributes
28 24 20 16 12 8 4 0 31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale ® processor Coprocessor address
CP6, Page 4, Register 1