Intel CONTROLLERS 413808 - Manual (Page 12)

Intel
®
413808 and 413812—Contents
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
12 Order Number: 317805-001US
4.7.26 MSI-X Capability Identifier Register - MSI-X_Cap_ID.................................435
4.7.27 MSI-X Next Item Pointer Register - MSI-X_Next_Item_Ptr..........................436
4.7.28 MSI-X Message Control Register - MSI-X_MCR..........................................437
4.7.29 MSI-X Table Offset Register — MSI-X_Table_Offset...................................438
4.7.30 MSI-X Pending Bit Array Offset Register - MSI-X_PBA_Offset......................439
4.7.31 MU MSI-X Control Register X — MMCRx ...................................................440
4.7.32 Inbound MSI Interrupt Pending Register x — IMIPRx .................................441
4.8 Power/Default Status .......................................................................................441
5.0 SRAM DMA Unit (SDMA) ............................................................................................442
5.1 Introduction....................................................................................................442
5.2 Overview........................................................................................................442
5.3 Theory of Operation .........................................................................................443
5.3.1 Interrupt Control for SDMA ....................................................................445
5.4 Register Definitions..........................................................................................446
5.4.1 LocalToHost Destination Lower Address Register - L2H_DLAR .....................447
5.4.2 LocalToHost Destination Upper Address Register - L2H_DUAR.....................447
5.4.3 LocalToHost Source Lower Address Register - L2H_SLAR............................448
5.4.4 LocalToHost Byte Count Register - L2H_BCR.............................................449
5.4.5 LocalToHost Interrupt Counter/Acknowledge Register L2H_ICAR .................450
5.4.6 LocalToHost Control/Status Register - L2H_CSR........................................451
5.4.7 LocalToHost Byte Swap Control Register - L2H_BSCR ................................452
5.4.8 HostToLocal Destination Lower Address Register - H2L_DLAR .....................452
5.4.9 HostToLocal Source Upper Address Register - H2L_SUAR ...........................453
5.4.10 HostToLocal Source Lower Address Register - H2L_SLAR............................453
5.4.11 HostToLocal Byte Count Register - H2L_BCR.............................................454
5.4.12 HostToLocal Interrupt Counter/Acknowledge Register - H2L_ICAR...............455
5.4.13 HostToLocal Control/Status Register - H2L_CSR........................................456
5.4.14 HostToLocal Byte Swap Control Register - H2L_BSCR ................................457
6.0 SGPIO Unit ..............................................................................................................458
6.1 Overview........................................................................................................458
6.2 Theory of Operation .........................................................................................460
6.2.1 SGPIO SClock Output Signal...................................................................460
6.2.2 SGPIO SLoad Output Signal ...................................................................460
6.2.3 SDataOut ............................................................................................461
6.2.4 SGPIO SDataIn Signal ...........................................................................461
6.3 Clock Requirements .........................................................................................462
6.4 Output Signals ................................................................................................463
6.4.1 Protocol Engine Input Signals .................................................................465
6.4.1.1 JOG Requirements...................................................................467
6.4.1.2 Protocol Engine Pre-Conditioning Requirements...........................467
6.4.2 Programmable Blink Patterns .................................................................468
6.5 SGPIO Unit Mode of Operations .........................................................................469
6.5.1 Pin Multiplexing....................................................................................472
6.6 Register Definitions..........................................................................................474
6.6.1 SGPIO Interface Control Register x — SGICRx ..........................................475
6.6.2 SGPIO Programmable Blink Register x — SGPBRx .....................................476
6.6.3 SGPIO Start Drive Lower Register x — SGSDLRx.......................................478
6.6.4 SGPIO Start Drive Upper Register x — SGSDURx ......................................480
6.6.5 SGPIO Serial Input Data Lower Register x — SGSIDLRx.............................482
6.6.6 SGPIO Serial Input Data Upper Register x — SGSIDURx.............................483
6.6.7 SGPIO Vendor Specific Code Register x — SGVSCRx..................................483
6.6.8 SGPIO Output Data Select Register[0:7] x — SGODSR[0:7]x......................484
7.0 System Controller (SC) and Internal Bus Bridge............................................................485