Intel CONTROLLERS 413808 - Manual (Page 497)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 497
System Controller (SC) and Internal Bus Bridge—Intel
®
413808 and 413812
7.4 System Controller Register Definitions
The following registers are located in the Peripheral Memory-Mapped Register (PMMR)
address space. They are accessible through the south internal bus accesses. The
Internal Bus Arbitration Control Register provides controls for both the North and South
Internal address busses. The south internal bus address and data test registers are
used to force address or data parity errors on the south internal bus respectively. Note
that the north internal bus does not support address and data parity.
• Internal Bus Arbitration Control Register
• South Internal Bus Address Test Register
• South Internal Bus Data Test Register
• Peripheral Memory-Mapped Register Base Address Register
The system controller only claims the address offset range +1640H through +164FH.