Intel CONTROLLERS 413808 - Manual (Page 63)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 63
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
The data flow for an inbound read transaction on the internal bus is summarized in the
following statements:
• The ATU internal bus master interface requests the internal bus when a PCI address
appears in an ITQ and transaction ordering has been satisfied. When operating in
the PCI-X mode the ATU does not use the information provided by the Relax
Ordering Attribute bit. That is, ATU always uses conventional PCI ordering rules.
• Once the internal bus is granted, the internal bus master interface drives the
translated address onto the bus. When a Retry is signaled, the request is repeated.
When a master abort occurs, the transaction is considered complete and a target
abort is loaded into the associated IRQ for return to the PCI initiator (transaction is
flushed once the PCI master has been delivered the target abort).
• Once the translated address is on the bus and the transaction has been claimed,
the internal bus target starts returning data using a split response. Read data is
continuously received by the IRQ until one of the following is true:
— The full byte count requested by the ATU read request is received. The internal
bus completer’s initiator interface performs an initiator completion in this case.
— A partial byte count requested by the ATU read request is received. The
completer’s internal bus initiator interface performs an initiator completion in
this case. Also, the completer reacquires the internal bus to deliver the
remaining read data byte count to the ATU.
— When operating in the conventional PCI mode, a Target Abort is received on the
internal bus from the internal bus target. In this case, the transaction is
aborted and the PCI side is informed.
— When operating in the PCI-X mode, a Target Abort is received on the internal
bus from the internal bus target. In this case, the transaction is aborted. The
ATU generates a Split Completion Message (message class=2h - completer
error, and message index=81h - internal bus target abort) on the PCI bus to
inform the requester about the abnormal condition. The ITQ for this transaction
is flushed.
To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be
programmed to ignore the memory read command (Memory Read, Memory Read Line,
and Memory Read Multiple) when trying to match the current inbound read transaction
with data in a DRC queue which was read previously (DRC on target bus). When the
Read Command Alias Bit in the ATUCR register is set, the ATU does not distinguish the
read commands on transactions. For example, the ATU enqueues a DRR with a Memory
Read Multiple command and performs the read on the internal bus. Some time later, a
PCI master attempts a Memory Read with the same address as the previous Memory
Read Multiple. When the Read Command Bit is set, the ATU would return the read data
from the DRC queue and consider the Delayed Read transaction complete. When the
Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI
read commands did not match, only the address.