80 root error command register - rerr_cmd, Table 220. root error command register - rerr_cmd, 80root error command register - rerr_cmd – Intel CONTROLLERS 413808 User Manual
Page 362: 220 root error command register - rerr_cmd, Pci express advanced error header, Log - adverr_log3, Root error command register - rerr_cmd, Transaction header log for pci express error, Intel, Bit default description
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
362
Order Number: 317805-001US
3.17.79 PCI Express Advanced Error Header Log - ADVERR_LOG3
Transaction header log for PCI Express error.
3.17.80 Root Error Command Register - RERR_CMD
The Root Error Command Register is used to notify the Intel XScale
®
processor in
response to PCI Express Error Messages. This bits enable or disable the generation of
the ATU Root Complex error interrupt.
Table 219. PCI Express Advanced Error Header Log - ADVERR_LOG3
Bit
Default
Description
31:0
0
4th DWord of the Header for the PCI Express packet in error.
Once an error is logged in this register, it remains locked for further error logging until the time the
software clears the status bit that cause the header log i.e. the error pointer is rearmed to log again.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
S S S S
S S S
S
S S S
S
S S S
S
S S S S
S S S
S
S S S S
S S S
S
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+128H
Table 220. Root Error Command Register - RERR_CMD
Bit
Default
Description
31:3
0000 0000H Preserved
2
0
Fatal Error Reporting Enable
When set, this bit enables the generation of the ATU Root Complex Error interrupt.
1
0
Non-Fatal Error Reporting Enable
When set, this bit enables the generation of the ATU Root Complex Error interrupt
0
0
Correctable Error Reporting
When set, this bit enables the generation of the ATU Root Complex Error interrupt
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
pr
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+12CH