Intel CONTROLLERS 413808 - Manual (Page 572)

Intel
®
413808 and 413812—Interrupt Controller Unit
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
572 Order Number: 317805-001US
10.5 The Intel
®
413808 and 413812 I/O Controllers in TPER
Mode Interrupt Controller Unit
The 4138xx Interrupt Controller Unit (ICU) provides a flexible, low-latency means for
requesting interrupts and minimizing the core’s interrupt handling burden.
All interrupt sources are combined into one of the two internal interrupt exceptions:
IRQ and FIQ.
The interrupt controller provides the following features for managing
hardware-requested interrupts:
• Flexibility to direct interrupt sources to either the FIQ or IRQ internal interrupt
exception
• 17 external interrupt pins.
— One high-priority interrupt pin, HPI# .
— Sixteen Maskable Inputs, XINT[15:0]# . Note that when the 4138xx acts as
an endpoint with the PCI-X interface, only twelve interrupt inputs
( XINT[15:4]# ) are available instead of sixteen, as the remaining four become
outputs ( P_INT[D:A]# ).
• Two internal timers sources.
• Peripheral interrupt sources.
• Two Intel XScale
®
processor interrupts.
All interrupts are level sensitive: interrupt sources must keep asserting the interrupt
signal until software causes the source to deassert it.
All interrupt sources are individually maskable with the ICUs Interrupt Control
registers.
Additionally, all interrupts may be quickly disabled by altering the F and I bits in the
CPSR as specified in the ARM Architecture Reference Manual.
When software running on the 4138xx is vectored to an Interrupt Service Routine
(ISR), it reads the ICUs IRQ Interrupt Vector Register (IINTVEC) or FIQ Interrupt
Vector register (FINTVEC) to quickly retrieve the address for the interrupt handler of
the highest priority active interrupt source.