Intel CONTROLLERS 413808 - Manual (Page 689)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 689
I 2 C Bus Interface Units—Intel ® 413808 and 413812
14.0 I
2
C Bus Interface Units
Note: I2C0 is owned by the Ttransport Core. See the System/Software Architecture
Specification for details on how to change this.
This chapter describes the three I
2
C (Inter-Integrated Circuit) bus interface units,
including the operation modes and setup. Throughout this manual, these peripherals
are referred to as the I
2
C units.
14.1 Overview
The three I
2
C Bus Interface Units allows the Intel
®
413808 and 413812 I/O Controllers
in TPER Mode (4138xx) to serve as a master and slave device residing on the I
2
C bus.
The I
2
C bus is a serial bus developed by Philips* Corporation consisting of a two-pin
interface. SDA is the data pin for input and output functions and SCL is the clock pin
for reference and control of the I
2
C bus.
The I
2
C bus allows the 4138xx to interface to other I
2
C peripherals and
microcontrollers for system management functions. The serial bus requires a minimum
of hardware for an economical system to relay status and reliability information on the
4138xx subsystem to an external device.
The I
2
C Bus Interface Unit is a peripheral device that resides on a 4138xx internal bus.
Data is transmitted to and received from the I
2
C bus via a buffered interface. Control
and status information is relayed through a set of memory-mapped registers. Refer to
the I
2
C Bus Specification for complete details on I
2
C bus operation.