Intel CONTROLLERS 413808 - Manual (Page 149)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 149
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.6 ATU Status Register - ATUSR
The ATU Status Register bits adhere to the PCI Local Bus Specification, Revision 2.3
definitions. The read/clear bits can only be set by internal hardware and cleared by
either a reset condition or by writing a 1
2
to the register.
Table 32. ATU Status Register - ATUSR (Sheet 1 of 2)
Bit Default Description
15 0
2
Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus
even when the ATUCMD register’s Parity Error Response bit is cleared. Set under the following
conditions:
• Uncorrectable Write Data Error when the ATU is a target (inbound write).
• Uncorrectable Read Data Error when the ATU is a requester (outbound read).
• Any Uncorrectable Address or Attribute (PCI-X Only) Error on the Bus (including one generated by
the ATU).
14 0
2
SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU.
13 0
2
Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort
or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode.
12 0
2
Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a
target abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode.
11 0
2
Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the
PCI bus with a target abort.
10:09 01
2
DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device
in Conventional PCI Mode regardless of the operating mode (except configuration accesses).
00
2
= Fast
01
2
= Medium
10
2
= Slow
11
2
= Reserved
The ATU interface uses Medium timing.
08 0
2
Master Parity Error - The ATU interface sets this bit under the following conditions:
• The ATU asserted PERR# itself or the ATU observed PERR# asserted.
• And the ATU acted as the requester for the operation in which the error occurred.
• And the ATUCMD register’s Parity Error Response bit is set
• Or (PCI-X Mode Only) the ATU received an Uncorrectable Write Data Error Message
• And the ATUCMD register’s Parity Error Response bit is set
07
1
2
(Conventional
mode)
0
2
(PCI-X mode)
Fast Back-to-Back - The ATU interface is capable of accepting fast back-to-back transactions in
Conventional PCI mode when the transactions are not to the same target. Since fast back-to-back
transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode.
06 0
2
UDF Supported - User Definable Features are not supported
05 1
2
66 MHz. Capable - 66 MHz operation is supported.
04 1
2
Capabilities - When set, this function implements extended capabilities.
PCI
IOP
Attributes
Attributes
15 12 8 4 0
rc
rc
rc
rc
rc
rc
rc
rc
rc
rc
ro
ro
ro
ro
rc
rc
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
rv
rv
rv
rv
rv
rv
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+006H