Intel CONTROLLERS 413808 - Manual (Page 664)

Intel ® 413808 and 413812—UARTs
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
664 Order Number: 317805-001US
13.3.2 Removing Trailing Bytes In Interrupt Mode
When the number of entries in the Receive FIFO is less than its trigger level, and no
additional data is received, the remaining bytes are called trailing bytes. When the
receive FIFO is being serviced by processor interrupts, trailing bytes need to be
removed via the processor using the 16550 compliant character time-out interrupt:
Time Out Detected (TOD) bit of Interrupt Identification Register. To enter this mode,
users need to insure that the character time-out interrupt is enabled via IER[4].
To remove trailing bytes in Interrupt mode, the user must wait for the character
time-out interrupt and then read all remaining bytes as indicated in the FIFO
Occupancy Register (FOR), or read one byte at a time until the FIFO is empty. This can
be determined by polling the Line Status Register bit 0 through programmed I/O.
13.3.2.1 Character Time-out Interrupt
When the Receiver FIFO and Receiver Time-out Interrupt are enabled, a character
time-out interrupt (TOD) occurs to signal the presence of trailing bytes. The Interrupt is
cleared and the timer is reset when a character is read from the Receiver FIFO. When a
time-out Interrupt has not occurred, the time-out timer is reset after a new character is
received or after the processor reads the Receiver FIFO.
When enabled via IER[4], a character time-out occurs under the following conditions:
• At least one character is in the FIFO.
• A character has not been received for the amount of time it takes to receive four or
more characters at the current baud rate.
• The FIFO has not been read for the amount of time it takes to receive four or more
characters
13.3.3 FIFO Polled Mode Operation
With the FIFOs enabled (TRFIFOE bit of FCR set to 1), clearing IER[7] and IER[4:0]
puts the serial port in the FIFO polled mode of operation. Since the receiver and the
transmitter are controlled separately, either one or both can be in the Polled Operation
mode. In this mode, software checks Receiver and Transmitter status via the LSR. The
processor polls the following bits for Receive and Transmit Data Service.
13.3.3.1 Receive Data Service
• Processor should check Data Ready bit of LSR which is set when 1 or more bytes
remains in the Receive FIFO or Receive Buffer register (RBR).
13.3.3.2 Transmit Data Service
• Processor should check Transmit Data Request bit of LSR which is set when
transmitter needs data.
• • Processor can also check Transmitter Empty bit of LSR, which is set when the
Transmit FIFO or Holding register is empty.