25 interrupt priority register 0 - ipr0, Table 407. interrupt priority register 0 - ipr0, 25interrupt priority register 0 — ipr0 – Intel CONTROLLERS 413808 User Manual
Page 619: 407 interrupt priority register 0 — ipr0, 25 interrupt priority register 0 — ipr0
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
619
Interrupt Controller Unit—Intel
®
413808 and 413812
10.7.25 Interrupt Priority Register 0 — IPR0
The Interrupt Priority Register 0 is a 32-bit Coprocessor 6 control register used to
assign a priority level to interrupt sources 15 down to 0. The IPR0 control register is
used to assign one of 4 priority levels to each interrupt source independent of the
INTSTR[3:0] registers:
When interrupt vector generation is enabled and there are multiple requests pending
either in the FINTSRC[3:0] or the IINTSRC[3:0] registers, the highest priority vectors
pending for either FIQ or IRQ are presented in the FINTVEC or IINTVEC respectively.
Note:
When multiple interrupts at the same priority level are pending for either FIQ or IRQ,
the vector is selected according to a fixed priority based on bit location. Highest order
bit is first.
00
2 —
High Priority
01
2 —
Medium/High Priority
10
2 —
Medium/Low Priority
11
2 —
Low Priority
Table 407. Interrupt Priority Register 0 — IPR0
Bit
Default
Description
31:30
00
2
ATU/Start BIST Interrupt Priority
29:28
00
2
ATU-E Inbound Message Interrupt Priority
27:26
00
2
Reserved.
25:24
00
2
Messaging Unit Interrupt Priority
23:22
00
2
I
2
C Bus Interface 1 Interrupt Priority
21:20
00
2
I
2
C Bus Interface 0 Interrupt Priority
19:18
00
2
Timer 1 Interrupt Priority
17:16
00
2
Timer 0 Interrupt Priority
15:14
00
2
Reserved.
13:12
00
2
Watch Dog Timer Interrupt Priority
11:10
00
2
Reserved.
09:08
00
2
Reserved.
07:06
00
2
Reserved.
05:04
00
2
Reserved.
03:02
00
2
Reserved.
01:00
00
2
Reserved.
Memory
Coprocessor
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na na
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Intel XScale
®
processor Coprocessor address
CP6, page 8, Register 0