Intel CONTROLLERS 413808 - Manual (Page 645)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 645
SMBus Interface Unit—Intel ® 413808 and 413812
12.3.2 SMBus Signaling
12.3.2.1 Overview
The SMBus interface includes a pair of signals: SMBCLK (clock) and SMBDAT (serial
data). SMBCLK provides the timing mechanism for data transfers. The SMBus master
always drives SMBCLK . The 4138xx may optionally extend SMBCLK low time by
driving it low to meet setup timings on the SMBus.
An initiator starts a transfer over the SMBus when it is free. Details of how initiators
arbitrate are not described here. The current initiator communicates to the desired
target through a unique 7-bit address to the target, sent MSb to LSb. All devices
monitor the generated address after detecting the start condition. Once seven address
bits are received, all targets compare the received address with their own and the
target slave finds a match.
The next data bit from the initiator indicates the transfer direction. A value of ‘1’
indicates that the target needs to transfer data to the initiator (read). Data transfers
over SMBus are performed in 8-bit chunks. Data is transferred from MSb to LSb.
12.3.2.2 Waveforms
The timing relationship between SMBDAT and SMBCLK is defined such as the
SMBDAT value must be valid through the duration of SMBCLK being in High state. The
following diagram illustrates data transfer:
12.3.2.2.1 Start Phase
A start condition is generated when SMBus is idle to indicate that its state is changing
to busy. The start condition occurs when SMBDAT transitions from High to Low while
SMBCLK remains High. The SMBus protocol also allows a master to “Repeat Start”,
meaning that a new transfer is started by the same master, without a stop condition.
Figure 73. Basic SMBus Transfer Waveform
Valid Valid Valid
SMBCLK
SMBDAT
B6276-01
Figure 74. Start (S) / Repeat Start (Sr) Signaling
SMBCLK
SMBDAT
B6277-01