Intel CONTROLLERS 413808 - Manual (Page 341)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 341
Address Translation Unit (PCI Express)—Intel
®
413808 and 413812
3.17.56 PCI Express Next Item Pointer Register - PCIE_NXTP
The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus
Specification, Revision 2.3. This register describes the location of the next item in the
function’s capability list.
By default, the PCI Express capability is the last capabilities list for the 4138xx, thus
this register defaults to 00H.
However, this register may be written to 90H prior to host configuration to include the
VPD capability located at off-set 90H.
Warning:
Writing this register to any value other than 00H (default) or 90H is not supported and
may produce unpredictable system behavior.
In order to insure that this register is written prior to host configuration, the 4138xx
must be initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of
PCSR). Typically, the Intel XScale
®
processor would be enabled to boot immediately
following P_RST# assertion in this case (bit 1 of PCSR), as well. Please see Section
3.17.41, “PCI Configuration and Status Register - PCSR” on page 327 for more details
on the 4138xx’s initialization modes.
Table 196. PCI Express Next Item Pointer Register - PCIE_NXTP
Bit Default Description
07:00 00H
Next_ Item_ Pointer - This field provides an offset into the function’s configuration space pointing to the
next item in the function’s capability list. Since the PCI Express capabilities are the last in the linked list
of extended capabilities in the 4138xx, the register is set to 00H.
However, this field may be written prior to host configuration with 90H to extend the list to include the
VPD extended capabilities header.
PCI
IOP
Attributes
Attributes
7 4 0
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
rw
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0D1H