Intel CONTROLLERS 413808 - Manual (Page 691)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 691
I 2 C Bus Interface Units—Intel ® 413808 and 413812
The I
2
C bus allows for a multi-master system, which means more than one device can
initiate data transfers at the same time. To support this feature, the I
2
C bus arbitration
relies on the wired-AND connection of all I
2
C interfaces to the I
2
C bus. Two masters can
drive the bus simultaneously provided they are driving identical data. The first master
to drive SDA high while another master drives SDA low loses the arbitration. The SCL
line consists of a synchronized combination of clocks generated by the masters using
the wired-AND connection to the SCL line.
The I
2
C bus serial operation uses an open-drain wired-AND bus structure, which allows
multiple devices to drive the bus lines and to communicate status about events such as
arbitration, wait states, error conditions and so on. For example, when a master drives
the clock ( SCL ) line during a data transfer, it transfers a bit on every instance that the
clock is high. When the slave is unable to accept or drive data at the rate that the
master is requesting, the slave can hold the clock line low between the high states to
insert a wait interval. The master’s clock can only be altered by a slow slave peripheral
keeping the clock line low or by another master during arbitration.
I
2
C transactions are either initiated by the 4138xx as a master or are received by the
processor as a slave. Both conditions may result in the processor doing reads, writes,
or both to the I
2
C bus.