Intel CONTROLLERS 413808 - Manual (Page 697)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 697
I 2 C Bus Interface Units—Intel ® 413808 and 413812
14.3 I
2
C Bus Operation
The I
2
C Bus Interface Unit transfers in 1 byte increments. A data transfer on the I
2
C
bus always follows the sequence:
1. START.
2. 7-bit Slave Address.
3. R/W# Bit.
4. Acknowledge Pulse.
5. 8 Bits of Data.
6. Ack/Nack Pulse.
7. Repeat of Step 5 and 6 for Required Number of Bytes.
8. Repeated START (Repeat Step 1) or STOP.
9. Serial Clock Line ( SCL ) Generation.
The 4138xx’s I
2
C unit is required to generate the I
2
C clock output when in master
mode (either receive or transmit). SCL clock generation is accomplished through the
use of the Fast Mode Enable bit, which is programmed at initialization. The following
equation is used to determine the SCL transition period:
14.3.1 Data and Addressing Management
Data and slave addressing is managed via the I
2
C Data Buffer Register (IDBR) and I
2
C
Slave Address Register (ISAR). IDBR (see Section 14.8.4, “I2C Data Buffer Register x
— IDBRx” ) contains data or a slave address and R/W# bit. ISAR contains the 4138xx
programmable slave address. Data coming into the I
2
C unit is received into IDBR after
a full byte is received and acknowledged. To transmit data, the processor writes to
IDBR, and the I
2
C unit passes this onto the serial bus when the Transfer Byte bit in the
ICR is set. See Section 14.8.1, “I2C Control Register x — ICRx” .
When the I
2
C unit is in transmit mode (master or slave):
1. Software writes data to the IDBR over the internal bus. This initiates a master
transaction or sends the next data byte, after the IDBR Transmit Empty bit is sent.
2. I
2
C unit transmits data from IDBR when the Transmit Empty bit in the ICR is set.
3. When enabled, an IDBR Transmit Empty interrupt is signalled when a byte is
transferred on the I
2
C bus and the acknowledge cycle is complete.
4. When the I
2
C bus is ready to transfer the next byte before the processor has
written the IDBR (and a STOP condition is not in place), the I
2
C unit inserts wait
states until the processor writes a new value into the IDBR and sets the ICR
Transfer Byte bit.
When the I
2
C unit is in receive mode (master or slave):
1. The processor reads the IDBR data over the internal bus after the IDBR Receive Full
interrupt is signalled.
2. I
2
C unit transfers data from shift register to IDBR after the Ack cycle completes.
3. The I
2
C unit inserts wait states until the IDBR is read. Refer to Section 14.3.2, “I2C
Acknowledge” on page 699 for acknowledge pulse information in receiver mode.
4. After processor reads IDBR, the I
2
C unit writes the ICRs Ack/Nack Control bit and
the Transfer Byte bit, allowing the next byte transfer to proceed.
Equation 18.SCL Transition Period
SCL Transition Period = (30 ns) * (167 - (Fast Mode Enable * 120))