Intel CONTROLLERS 413808 - Manual (Page 523)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 523
SRAM Memory Controller—Intel
®
413808 and 413812
Figure 59 shows how the data flows through the ECC hardware for a read transaction.
Figure 59. ECC Read Data Flow
ECC
256 - bit Data Path
SMCU
SRAM Memory Array
ECC
Memory
D[31:0]
H-Matrix
Look-Up
Table
Caculate
ECC
(G-Matrix)
Caculate
Syndrome
Data
Corrector
(single-bit error)
Error Type
and Location
H-Matrix
Look-Up
Table
Caculate
ECC
(G-Matrix)
Caculate
Syndrome
Data
Corrector
(single-bit error)
Error Type
and Location
Memory
D[255:224]
B6359-01