Intel CONTROLLERS 413808 - Manual (Page 549)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 549
Peripheral Bus Interface Unit—Intel
®
413808 and 413812
9.2.5 Detailed Signal Descriptions
Bus signal descriptions are detailed in Table 362 .
Table 361. Bus Signal Descriptions
NAME DESCRIPTION
D[15:0]
DATA BUS carries 16-bit physical addresses and 8-, or 16-bit data to and from memory.
During a data (T
d
) cycle, bits 0-7, or 0-15 contain read or write data, depending on the
corresponding bus width.
During write operations to 8-bit wide memory regions, the PBI drives unused bus pins
high or low.
A[24:0]
ADDRESS BUS 24:0 carries the 25-bit address bus which allows the PBI to address up
to 32 MBytes per peripheral device. During an address (T
a
) cycle, bits A[2:0] contains
the starting address of the access. During a bursted read data (T
d
) cycle, A[2:0]
represents the current byte address in the bursted transaction. Address bits A[24:3]
provide the upper address of the current access and is a constant during the address
(T
a
), wait state (T
w
) and data cycles (T
d
) cycles.
A[2:1] are used for an 16-bit wide peripheral while A1:0 are used for an 8-bit wide
peripheral.
POE#
PERIPHERAL OUTPUT ENABLE specifies, during a T
a
cycle, whether the operation is a
write (1) or read (0). It is latched on-chip and remains valid during T
d
cycles.
This signal is used as an OUTPUT ENABLE signal (OE#) for Peripheral Devices.
PCE[1:0]#
PERIPHERAL CHIP ENABLES 1:0 specify, during a T
a
cycle, which of the two Memory
Address Ranges are associated with the current bus access. It remains valid during T
d cycles
PWE#
PERIPHERAL WRITE ENABLE indicates to a peripheral device whether or not to use
the data on the D15:0 bus to write the addressed space. It is low during T
w
cycles and
deasserts during the T
d
cycle for a write; it is high during T
a
and T
w
/T
d
cycles for a read.
PB_RSTOUT#
PERIPHERAL BUS RESET can be used to reset the peripheral device. PB_RSTOUT#
has the same timings as the internal bus reset signal.