Intel CONTROLLERS 413808 - Manual (Page 710)

Intel ® 413808 and 413812—I 2 C Bus Interface Units
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
710 Order Number: 317805-001US
14.5.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master
1. Write IDBR: Target slave address and R/W# bit (0 for write)
2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)
Clear IDBR Transmit Empty bit to clear the interrupt.
4. Send byte 1
Write IDBR: With data byte to send
Write ICR: Clear START bit, Clear STOP bit, Enable Arb Loss interrupt, Set Transfer
Byte bit to initiate the access
5. Wait for Buffer empty interrupt.
Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)
Clear IDBR Transmit Empty bit to clear the interrupt.
6. Send byte 2
Write IDBR: With data byte to send
Write ICR: Clear START bit, Clear STOP bit, Set Transfer Byte bit to initiate the
access
7. Wait for Buffer empty interrupt.
Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (clear)
Clear IDBR Transmit Empty bit to clear the interrupt.
8. Send repeated start as a master
Write IDBR: Target slave address and R/W# bit (1 for read)
Write ICR: Set START bit, Clear STOP bit, Disable Arb Loss interrupt, Set Transfer
Byte bit the initiate the access
9. Wait for IDBR Transmit Empty interrupt. When interrupt comes.
Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (set)
Clear IDBR Transmit Empty bit to clear the interrupt.
10.Read byte with STOP
Write ICR: Clear START bit, Set STOP bit, Enable arb loss interrupt, Set Ack/Nack
bit (Nack), Set Transfer Byte bit to initiate the access
11.Wait for Buffer full interrupt. When interrupt comes (Note: Unit is sending STOP).
Read status register: IDBR Receive Full (set), Unit busy (set - maybe), R/W# bit
(Set), Ack/Nack bit (Set)
Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional)
Wait until Unit busy is clear before clearing the ICR SCL Enable bit. (optional)