Intel CONTROLLERS 413808 - Manual (Page 631)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 631
Timers—Intel ® 413808 and 413812
11.2 Timer Interrupts
Each timer is the source for one interrupt. When a timer detects a zero count in its
TCRx, the timer generates an internal level-detected Timer Interrupt signal (TINTx) to
the interrupt controller, and the interrupt source (INTSRC[1:0]) bit is set in the
interrupt controller. Each timer interrupt can be selectively masked in the Interrupt
Control (INTCTL[1:0]) registers. Refer to the Interrupt Controller Unit Chapter for a
description of interrupt controller operation.
After servicing the timer interrupt, the interrupt service routine clears the pending
request by writing a ‘1’ to the appropriate bit of the Timer Interrupt Status Register
(TISR).
When a timer generates a second interrupt request before the CPU services the first
interrupt request, the second request may be lost.
When auto-reload is enabled for a timer, the timer continues to decrement the value in
TCRx even after entry into the timer interrupt handler.