Intel CONTROLLERS 413808 - Manual (Page 44)

Intel
®
413808 and 413812—Introduction
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
44 Order Number: 317805-001US
1.5 Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Features
The 81348 combines two Intel XScale
®
processors with powerful new features to
create an intelligent I/O storage processor. This single- or multi-function PCI device is
fully compliant with the PCI-X 2.0a and PCI Express 1.0a specifications. The
81348-specific features include:
The 81348 microarchitecture is based upon two Intel XScale
®
processors. When in
TPER mode, one processor is available for general application purposes (RAID). When
in IOC mode, there are no processors available. The microarchitecture operates at a
maximum frequency of 1.5 GHz. The instruction cache is 32 Kbytes in size and is
32-way set associative. Also, the microarchitecture includes a data cache that is
32 Kbytes and is 32-way set associative and a mini data cache that is 2 Kbytes and is
2-way set associative. Both Intel XScale
®
processors support unified 512-KByte Level 2
(L2) cache and is 8-way set associative.
The 81348 includes sixteen General Purpose I/O (GPIO) pins, which are used for SAS
Links for activity and status indicators. Each SAS link uses two LSO pins. The 81348
also supports two SGPIO busses.
The subsections that follow briefly overview each feature. Refer to the appropriate
chapter for full technical descriptions.
1.5.1 Host Interface
The 4138xx present a single function to the host When in IOC mode, the TPMI is
exposed to the host and PCI configuration parameters are setup by the Transport
Firmware. Some parameters are changed via use of the OEM Parameter Tool. When in
TPER mode, the TPMI is not exposed to the host, the ATU is. Thus, Application Core
firmware is fully responsible for setting up PCI configuration space.
1.5.2 Intel XScale
®
Processor
The Intel XScale
®
processor operates at a maximum frequency of 1.5 GHz. The
instruction cache is 32 Kbytes in size and is 32-way set associative. Also, the processor
includes a data cache that is 32 Kbytes and is 32-way set associative. The Intel
XScale
®
processor supports a unified 512-KByte Level 2 (L2) cache and is 8-way set
associative.
• Address Translation Unit • Performance Monitoring Unit
• Messaging Unit • Two Serial Port Units (UARTs)
• Peripheral Bus Interface Unit (PBI) • Inter-Processor Communication
• Three I
2
C Bus Interface Units • Two Programmable Timers per core
• Two SGPIO Busses • Watchdog Timers
• Internal Bus Bridge • Third Party Messaging Interface (TMPI)