Intel CONTROLLERS 413808 - Manual (Page 782)

Intel ® 413808 and 413812—Test Logic Unit and Testability
Intel ® 413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual October 2007
782 Order Number: 317805-001US
18.0 Test Logic Unit and Testability
18.1 Overview
This chapter summarizes testability and configuration features incorporated in the
Intel
®
413808 and 413812 I/O Controllers in TPER Mode (4138xx).
The 4138xx test and control logic is based on the IEEE 1149.1-2001 Standard Test
Access Port and Boundary-Scan Architecture document (available from the IEEE). The
TAP controller supports on-chip test logic such as Built-In Self Test and boundary-scan.