Intel CONTROLLERS 413808 - Manual (Page 525)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 525
SRAM Memory Controller—Intel
®
413808 and 413812
Referring to Figure 59 , the syndrome bits are created by XORing the ECC code bits as
indicated by the appropriate row of the G-Matrix in Figure 58 with the corresponding
ECC bits read from memory. For example, the SMCU derives syndrome bit 0 by XORing
ECC code associated with data bits 0, 2, 5, 8…15, 17, 20, 22, 24, 26, 28 and ECC bit 0
(physically read on SCB[0] ). The SMCU performs seven such XOR operations (one per
syndrome bit).
If decoding the syndrome indicates multi-bit error (see
Table 346 ), the transaction
results in a target-abort for Internal Bus transactions, or a multi-bit error in the BIU for
Core transactions. If an internal bus master detects a target-abort, the master asserts
an interrupt to the core. Write cycles are posted to the memory transaction queues,
and already completed to the initiating master. For write cycles with a multi-bit error
and ECC Error reporting is enabled, the SMCU reports the interrupt in the MCISR and
interrupts the core.
If the syndrome indicates a single-bit error and single-bit error correction is enabled,
the H-Matrix is used to determine the bit in error (see Figure 60 ). For example, if the
syndrome was 100 1001, the error is with bit 0 of DQ[31:0] . The SMCU inverts bit 0
before driving the data on internal bus.
If error reporting is enabled in the SECCR and the SMCU detects a single-bit or
multi-bit error, the SMCU stores the address in SECAR and the syndrome in SELOG.
Then, the SMCU signals an interrupt to the core. Software decides how to proceed
through an interrupt handler. By registering the address in SECAR, software can
identify the faulty location.
For details about the SMCU error conditions and how the MMR registers are affected,
refer to Section 8.4, “ECC Interrupts/Error Conditions” on page 531 .