Intel CONTROLLERS 413808 - Manual (Page 111)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 111
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.7.6 Target Aborts on the PCI Interface
As an initiator on the PCI bus, the ATU can encounter target abort conditions during:
• Outbound Read Request
• Outbound Write Request
• Inbound Read Completion
• Inbound Configuration Write Completion Message
As a target, the ATU PCI interface is capable of signaling a target abort case during:
• Inbound Read Request (PCI-X and Conventional Modes)
• Inbound Write Request to EROM memory space (PCI-X and Conventional Modes)
2.7.6.1 Target Aborts for Outbound Read Request or Outbound Write Request
This error can be encountered by the ATU in both the Conventional and PCI-X modes.
For an Outbound transaction, there are two ways in which a Target-Abort may be
signaled to the ATU:
1. In the Conventional or PCI-X modes, a target abort is signaled when the target of
the transaction simultaneously deasserts DEVSEL# , deasserts TRDY#, and
asserts STOP# .
2. In PCI-X mode, ATU may enqueue a Split request (Read or Write) on target-side
interface of a PCI-to-PCI Bridge. When PCI-to-PCI Bridge detects a Target Abort on
requester-side interface for that Split Request, target abort is signaled to ATU
through a Target-Abort Split Completion Error Message (class=1h - bridge error
and index=01h - Target Abort). The following actions with the given constraints are
performed by the ATU when a target abort is detected by the PCI initiator interface
or the PCI target interface receives a Target-Abort Split Completion error message:
• Set the Target Abort (master) bit (bit 12) in the ATUSR.
• When the ATU PCI Target Abort (master) Interrupt Mask bit in the ATUIMR is clear,
set the PCI Target Abort (master) bit in the ATUISR. When set, no action.
• When the transaction is an MSI outbound write and the SERR# Enable bit in the
ATUCMD is set, assert SERR# ; otherwise, no action is taken. When the ATU asserts
SERR#, additional actions are taken:
— Set the SERR# Asserted bit in the ATUSR.
— When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set
the SERR# Asserted bit in the ATUISR. When set, no action.
— When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set
the SERR# Detected bit in the ATUISR. When clear, no action.
• When operating in the PCI-X mode and the Target-Abort is signaled via a Split
Completion Error Message, the Received Split Completion Error Message bit in the
PCIXSR is set. When the ATU sets this bit, additional actions are taken:
— When the ATU Received Split Completion Error Message Interrupt Mask bit in
the ATUIMR is clear, set the Received Split Completion Error Message bit in the
ATUISR. When set, no action.
• For an Outbound Read request, the read completion is aborted on the internal bus.
• Flush the address from the OTQ.