54 atu scratch pad register - atuspr, Table 194. scratch pad register - atuspr, 54atu scratch pad register - atuspr – Intel CONTROLLERS 413808 User Manual
Page 340: 194 scratch pad register - atuspr, Ster, Section 3.17.55, Intel, Bit default description, 00 10h cap_id
Intel
®
413808 and 413812—Address Translation Unit (PCI Express)
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
Developer’s Manual
October 2007
340
Order Number: 317805-001US
3.17.54 ATU Scratch Pad Register - ATUSPR
This register can be used for application specific purposes and has no direct impact on
the hardware.
3.17.55 PCI Express Capability List Register - PCIE_CAPID
The Capability Identifier Register bits adhere to the definitions in the PCI Express Base
Specification, Revision 1.0a. This is the PCI Express Capability List with an ID of 10H as
defined by the PCI-X Protocol Addendum to the PCI Local Bus Specification,
Revision 2.0.
Table 194. Scratch Pad Register - ATUSPR
Bit
Default
Description
31:0
0000H
Scratch Pad Data - Entire register is available for application specific purposes.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0CCH
Table 195. PCI Express Capability Identifier Register - PCIE_CAPID
Bit
Default
Description
07:00
10H
Cap_Id
- This field with its’ 10H value identifies this item in the linked list of Extended Capability
Headers as being the PCI Express Capability List registers.
PCI
IOP
Attributes
Attributes
7
4
0
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
ro
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Internal Bus Address Offset
+0D0H