Intel CONTROLLERS 413808 - Manual (Page 709)

Intel ® 413808 and 413812 I/O Controllers in TPER Mode
October 2007 Developer’s Manual
Order Number: 317805-001US 709
I 2 C Bus Interface Units—Intel ® 413808 and 413812
14.5 Master Programming Examples
14.5.1 Initialize Unit
1. Write ISAR: Set slave address
2. Write ICR: Enable all interrupts (except Arb Loss), set SCL Enable, set Unit Enable
14.5.2 Write 1 Byte as a Master
1. Write IDBR: Target slave address and R/W# bit (0 for write)
2. Write ICR: Set START bit, Clear STOP bit, Set Transfer Byte bit to initiate the access
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read status register: IDBR Transmit Empty (set), Unit Busy (set), R/W# bit (clear)
Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.
Note: Arbitration Loss Detected bit may be set. When arbitration was lost, because Arb Loss
interrupt was disabled, an address retry occurs when bus becomes free. Clear
Arbitration Loss Detected bit when set.
4. Send byte with STOP
Write IDBR: With data byte to send
Write ICR: Clear START bit, Set STOP bit, Enable Arb Loss interrupt, Set Transfer
Byte bit to initiate the access
5. Wait for Buffer empty interrupt. When interrupt arrives (Note: Unit is sending
STOP):
Read status register: IDBR Transmit Empty (set), Unit busy (set - maybe), R/W#
bit (clear)
Clear IDBR Transmit Empty Interrupt bit to clear the interrupt.
Clear ICR STOP bit (optional)
Wait until Unit busy is clear before clearing the ICR SCL Enable bit.
14.5.3 Read 1 Byte as a Master
1. Write IDBR: Target slave address and R/W# bit (1 for read)
2. Write ICR: Set START bit, Clear STOP bit, Disable Arb loss interrupt, Set Transfer
Byte bit to initiate the access
3. Wait for IDBR Transmit Empty interrupt. When interrupt arrives:
Read status register: IDBR Transmit Empty (set), Unit busy (set), R/W# bit (set)
Clear IDBR Transmit Empty bit to clear the interrupt.
4. Read byte with STOP
Write ICR: Clear START bit, Set STOP bit, Enable arb loss interrupt, Set Ack/Nack
bit (Nack), Set Transfer Byte bit to initiate the access
5. Wait for Buffer full interrupt. When interrupt arrives (Note: Unit is sending STOP):
Read status register: IDBR Receive Full (set), Unit Busy (set - maybe), R/W# bit
(Set), Ack/Nack bit (Set)
Clear IDBR Receive Full bit to clear the interrupt.
Read IDBR data.
Clear ICR STOP bit (optional), Clear ICR Ack/Nack Control bit (optional)
Wait until Unit busy is clear before clearing the ICR SCL Enable bit. (optional)