28 inbound atu limit register 0 - ialr0, Table 55. inbound atu limit register 0 - ialr0, 28inbound atu limit register 0 - ialr0 – Intel CONTROLLERS 413808 User Manual
Page 169: 55 inbound atu limit register 0 - ialr0, Address translation unit (pci-x)—intel, Bit default description
Intel
®
413808 and 413812 I/O Controllers in TPER Mode
October 2007
Developer’s Manual
Order Number: 317805-001US
169
Address Translation Unit (PCI-X)—Intel
®
413808 and 413812
2.14.28 Inbound ATU Limit Register 0 - IALR0
Inbound address translation for memory window 0 occurs for data transfers occurring
from the PCI bus (originated from the PCI bus) to the 4138xx internal bus. The address
translation block converts PCI addresses to internal bus addresses.
The inbound translation base address for inbound window 0 is specified in
. When determining block size requirements — as described in
— the translation limit register provides the block size requirements for
the base address register. The remaining registers used for performing address
translation are discussed in
The 4138xx value register’s programmed value must be naturally aligned with the base
address register’s programmed value. The limit register is used as a mask; thus, the
lower address bits programmed into the 4138xx value register are invalid. Refer to the
PCI Local Bus Specification, Revision 2.3 for additional information on programming
base address registers.
Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12,
with a one to one correspondence. A value of 0 in a bit within the IALR0 makes the
corresponding bit within the IABAR0 a read only bit which always returns 0. A value of
1 in a bit within the IALR0 makes the corresponding bit within the IABAR0 read/write
from PCI. Note that a consequence of this programming scheme is that unless a valid
value exists within the IALR0, all writes to the IABAR0 has no effect since a value of all
zeros within the IALR0 makes the IABAR0 a read only register.
Note:
Bit 0 can be used to disable claiming of Memory Cycles that hit Inbound Memory
Window 0 even though the host processor has allocated memory of the size requested
by IABAR0/IALR0[31:12].
.
Table 55. Inbound ATU Limit Register 0 - IALR0
Bit
Default
Description
31:12
FF000H
Inbound Translation Limit 0 - This value determines the memory block size required for inbound
memory window 0 of the address translation unit. This defaults to an inbound window of 16MB.
11:01
000H
Reserved
00
0
2
Memory Window 0 Claim Disable -- When this bit is set, Inbound Memory Window 0 does not claim
memory cycles on the PCI Bus. When clear, Inbound Memory Window 0 claims PCI Memory Cycles
Normally.
PCI
IOP
Attributes
Attributes
28
24
20
16
12
8
4
0
31
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rv
rw
rw
Attribute Legend:
RV = Reserved
PR = Preserved
RS = Read/Set
RW = Read/Write
RC = Read Clear
RO = Read Only
NA = Not Accessible
Register Offset
+040H